Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a data output circuit of a semiconductor memory device.
In general, a data input/output of a synchronous semiconductor memory device is operated in synchronism with an internal clock signal generated on the basis of an external clock signal. Such a synchronous semiconductor memory device may be an SDR (Single Data Rate) SDRAM (Synchronous Dynamic Random Access Memory), which outputs data in synchronism with a rising edge of the internal clock signal. Alternatively, the synchronous semiconductor memory device may be a DDR (Double Data Rate) SDRAM, a DDR2 SDRAM, or a DDR3 SDRAM, which output data in synchronism with rising and falling edges of the internal clock signal.
A DDR3 SDRAM generally uses an 8-bit pre-fetch scheme. The 8-bit pre-fetch scheme is a method that, in the event that a read command is once generated inside of a semiconductor memory device, outputs 8-bit data in parallel from a memory cell array and then outputs the 8-bit data in series to an external device through one data input/output pin during 2 clock cycles.
A data output circuit of a known synchronous semiconductor memory device may include an alignment control signal generating unit and a pipe latch unit.
The alignment control signal generating unit may generate even alignment control signals SOSEB1_R and SOSEB2_R, and odd alignment control signals SOSEB1_F and SOSEB2_F in response to a column address applied with a read command during a read operation. The pipe latch unit may store 8-bit parallel data GIO<0:7> input from banks, and then may align the stored data in response to the even alignment control signals SOSEB1_R and SOSEB2_R, and the odd alignment control signals SOSEB1_F and SOSEB2_F, thereby outputting the aligned data in series.
For reference, the odd alignment control signals SOSEB1_F and SOSEB2_F may be generated by delaying the even alignment control signals SOSEB1_R and SOSEB2_R or inverted signals of the even alignment control signals SOSEB1_R and SOSEB2_R by a half clock of the internal clock signal.
Further, the pipe latch unit may include an even data alignment unit and an odd data alignment unit to determine a read burst order. The even data alignment unit may align the parallel data in response to the even alignment control signals SOSEB1_R and SOSEB2_R to output a first alignment-output data, and the odd data alignment unit may align the parallel data in response to the odd alignment control signals SOSEB1_F and SOSEB2_F to output a second alignment-output data.
FIG. 1 illustrates a circuit diagram of an even data alignment unit in a data output circuit of a known synchronous semiconductor memory device.
For reference, since a circuit configuration of the odd data alignment unit is substantially the same as the even data alignment unit except for input signals, its detailed description will be omitted for conciseness.
The even data alignment unit 10 includes a first-stage multiplexer 12 and a second-stage multiplexer 14 to perform a 2-step multiplexing operation. The first-stage multiplexer 12 selects one of even data DO01R and even data D023R, and one of even data D045R and even data DO67R in response to a first even alignment control signal SOSEB1_R. The second-stage multiplexer 14 selects one of outputs of the first-stage multiplexer 12 in response to a second even alignment control signal SOSEB2_R to output a first alignment-output data ARDO.
As described above, a known pipe latch unit may perform the 2-step multiplexing operation by sequentially controlling the first-stage multiplexer 12 and the second-stage multiplexer 14 in response to the even alignment control signals SOSEB1_R and SOSEB2_R or the odd alignment control signals SOSEB1_F and SOSEB2_F. As a result, the known pipe latch unit can determine a read burst order of output data. However, the likelihood of an asynchronous path is increased due to the above 2-step multiplexing operation, and this affects a column address access time (“tAA”), which is a performance factor representing the speed of data to be outputted from a read command. Furthermore, since each of the even and odd data alignment units is composed of the 2-stage multiplexer, a skew may occur due to the increased likelihood of an asynchronous path.